1. Field of the Invention
This invention relates to a MOS logic circuit suitable for circuit integration technology.
2. Brief Description of the Prior Art
In the conventional inverter circuit implemented with MOS circuit integration technology, as illustrated in FIG. 1, a driver MOS transistor T.sub.1 ' is operatively coupled with a load MOS transistor T.sub.2 ' such that an input signal is applied to the gate of the driver MOS transistor T.sub.1 ' via the point A' and then an output signal is derived from the joint terminal B' of the transistors T.sub.1 ' and T.sub.2 '. The curve of FIG. 2 shows the input-output characteristic of such inverter circuit. When the input signal is below a given level, the driver MOS transistor T.sub.1 ' is not conducting and the output signal at the point B is held at the constant value. If the input signal at the point A' exceeds the threshold level of the MOS transistor T.sub.1 ', current will begin to flow through the MOS transistor T.sub.1 ' at the point (I) and thereby to initiate logical inversion of the input signal. If the input signal at the point A' reaches the value as designated by the point (II), the output signal at the point B' will show the value as designated by the point (III), thereby logically inverting the next succeeding circuit connected to the point B'. Accordingly, the boundary level between the logical 1 and 0 with respect to the input signals to the point A' is limitedly placed adjacent the threshold level of the MOS transistor T.sub.1 ' which is largely determined pursuant to conditions of fabrication of MOS integrated circuit. Modification of the logical boundary or slice level of the input signal to the point A' requires the necessity for altering the threshold level of the MOS transistor T.sub.1 ' during the fabrication process and thus providing an additional process therefor.